486 Bench Contest

Interpreting the printout
-------------------------


CACHECHK v3beta2 11/11/95  Copyright (c) 1995 by Ray Van Tassle. (-h for help)
****** WARNING *******
	CPU is in V86 mode!	Timings may not be accurate!
CMOS reports: conv_mem= 640K, ext_mem= 15,360K, Total RAM= 16,000K
### This is the memory size, as listed in the CMOS (via setup)


"GenuineIntel" 486DX4 100 MHz
### The cpu type & speed.  Advanced CPUs will identify themselves. For
### others, the type is derived.
### The speed is determined by instruction timing, and is fairly accurate
### (plus/minus 3 mhz) from 386/16 to P5/120.


Reading from memory.  
MegaByte#:      --------- Memory Access Block sizes (KB)-----
       1    2    4    8   16   32   64  128  256  512 1024 2048 4096 <-- KB
 0:   11   11   11   11   11   20   20   20   20   28   --   --   --    æs/KB
### "n:" is the megabyte number. 0 = base memory, 1 = 2nd MB, etc.
### The numbers are how many microseconds it takes to read/write a certain
### number of bytes.
### We can see that 1KB through 16KB takes 11us/KB, 32KB through 256KB takes
### 20us/KB, and 512 KB takes 28us/KB.  This is the base memory, so we can't
### go beyond 640KB. So we stop at 512KB.
### The "--" (for blocks of 1MB, 2MB, and 4MB) means that blocks of this size
### were not tested (because they could not be).
### I go up to 4MB, because some lucky folks have 1MB of cache, and if I 
### stopped at a 2MB block, there is only one data point of RAM speed.


 2:   11   11   11   11   11   20   20   20   20   28   28   28   28    æs/KB
### Megabyte #1 is skipped here.  Because I have a memory manager (QEMM)
### loaded.  It occupies some of the memory at the beginning of MB#1, therefore
### this MB cannot be allocated, therefore I don't test it.
### However, I can check a blocksize of 4MB.  This means that it reads from
### address 0x0200000 through 0x05fffff.
### We now have 4 data-points of actual RAM speed.
### By inspection, we see that there are two breakpoints in the memory
### access speed.  The first at 16kb, the second at 256kb.  This is as it
### should be, as this is an Intel 486/100 (with 16kb of L1 cache), and 256kb
### of L2 cache on the motherboard.  An AMD 486/100 has 8KB of L1 cache.
### A Pentium has 8kb data cache and 8kb of instruction cache.
### CACHECHK only tests data, so P5's will show 8kb of L1 cache.


 3  4  5  6  7  8  9  <--- same as above.
### The speeds of megabyte 2 thru megabyte 9 are all the same.
### Actually, this is a small fib.  Since mb#9 is the last full mb being
### tested, we clearly can't be using block sizes of 2MB or 4MB.  And for
### mb#8, we can't use block size of 4MB.  Those entries actually have
### "--".  But the numbers which *are* there are the same.


 This machine seems to have both L1 and L2 cache. [read]
### This is reading.  Writing will say ["write]".
    L1 cache is  16KB -- 103.3 MB/s  10.2 ns/byte  (262%) (186%)   3.9 clks
    L2 cache is 256KB --  55.3 MB/s  19.0 ns/byte  (140%) (100%)   7.2 clks
    Main memory speed --  39.3 MB/s  26.7 ns/byte  (100%) [read]  10.2 clks
	L1 cache is  16KB --	102.8 MB/s  10.2 ns/byte  (261%)  (185%)
	L2 cache is 256KB --	 55.3 MB/s  19.0 ns/byte  (140%)  (100%)
	Main memory speed --	 39.3 MB/s  26.7 ns/byte  (100%) [read]
### The L1 cache is 262% (two and a half times) faster than RAM.
### The L2 cache is 140% (one and a half times) faster than RAM.
### The L1 cache is 186% faster (almost twice as fast) as the L2 cache.
### It takes an average of 3.9 clock cycles to read a 32-bit longword from
### the L1 cache into a 32-bit register, 7.2 cycles from L2, and 10.2 from RAM.


	Effective read RAM access time is 106ns (a RAM bank is 4 bytes wide). 
### This is the *measured* access speed of the RAM.  On a 486, this
### is 4 times the "main memory speed" (above example is 4 * 26.7), because
### a 486 has a 32-bit (4 byte) path between RAM and the CPU.  For a P5,
### this will be 8 times, because the P5 has a 64-bit (8 byte) path.
### Note that this is NOT the speed of your RAM chips---it is the measure of
### how fast your RAM is being driven.  
###
### This is VERY dependent on the "DRAM Burst Cycle" settings in your BIOS
### setup.  This computer has an AMI bios, where I can set it to certain
### values.  The fastest it will allow is 3-2-2-2.  The slowest
### it will allow is 5-4-4-4.  With this slow setting, I get:
###	Main memory speed --	 24.9 MB/s  42.1 ns/byte  (100%) [read]
###	Effective read RAM access time is 168ns (a RAM bank is 4 bytes wide). 
### This is much slower, BUT it might let me use slower (i.e., cheaper) RAM
### chips.
### Note that *many* motherboards will NOT let you fiddle with these settings.
### The 486 (and Pentium) always fill the entire cache line (16 bytes), so
### it is NOT possible to get just one byte from the memory; it always
### grabs all 16 bytes in that block.